The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasing interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.
Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. Innovations in front-end process technologies or the introduction of alternative device structures will sustain the historical pace of device scaling.
For device scaling well into the sub-30-nm regime, a promising approach to controlling short-channel effects is to use an alternative transistor structure with more than one gate, i.e. multiple-gates. An example of the alternative transistor structure is the multiple-gate transistor. A multiple-gate transistor 100 has a plan view as shown in FIG. 1.
Referring to FIG. 1, the transistor 100 includes a silicon fin 102 overlying an insulator layer 104 over a silicon substrate 114 (see FIGS. 2a, 2b or 2c). A gate dielectric (not explicitly shown) covers a portion of the silicon fin 102. A gate electrode 106 straddles across the silicon fin 102. The gate dielectric isolates the gate electrode 106 from the silicon fin 102.
Examples of the multiple-gate transistor include the double-gate transistor (as shown in U.S. Pat. No. 6,391,695, and X. Huang et al., “Sub-50 nm p-channel finFET,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880-886, May 2001), triple-gate transistor (as shown in R. Chau et al., “Advanced depleted-substrate transistors: single-gate, double-gate, and tri-gate”, 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, pp. 68-69, September 2002), omega field-effect transistor (FET) (as shown in F.-L. Yang et al., “25 nm CMOS Omega-FETs,” International Electron Device Meeting, Dig. Technical Papers, December 2002), and the surround-gate or wrap-around gate transistor (as shown in J. P. Colinge et al., “Silicon-on-insulator gate-all-around device,” International Electron Device Meeting, Dig. Technical Papers, pp. 595-598, December 1990 and E. Leobandung et al., “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects,” J. Vacuum Science and Technology B, vol. 15, no. 6, pp. 2791-2794, 1997). Each of these references is incorporated herein by reference.
A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
The simplest example of a multiple-gate transistor is the double-gate transistor, as described in U.S. Pat. No. 6,413,802 issued to Hu, et al. U.S. Pat. No. 6,413,802 is incorporated herein by reference. As illustrated in a cross-sectional view in FIG. 2a, the double-gate transistor 100 has a gate electrode 106 that straddles across the channel within the fin-like silicon body 102, thus forming a double-gate structure. There are two gates, one on each sidewall 108 of the silicon fin 102, and separated from the fin 102 by gate dielectric 110. An etchant mask 112 overlies a top surface of fin 102. The plan view of the double-gate structure is shown in FIG. 1.
In U.S. Pat. No. 6,413,802, the transistor channel comprises a thin silicon fin defined using an etchant mask and formed on an insulator layer, e.g. silicon oxide. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate structure overlying the sides of the fin. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface.
Another example of the multiple-gate transistor is the triple-gate transistor. A cross-section of the triple-gate transistor 100′ is illustrated in FIG. 2b and thus the plan view of the triple-gate structure is the same as the double gate structure shown in FIG. 1. The triple-gate transistor structure 100′ has a gate electrode 106 that forms three gates: one gate on the top surface 116 of the silicon body/fin 102, and two gates on the sidewalls 108 of the silicon body/fin 102. The triple-gate transistor achieves better gate control than the double-gate transistor because of it has one more gate on the top of the silicon fin.
The triple-gate transistor structure may be modified for improved gate control, as illustrated in FIG. 2c. Such a structure 100″ is also known as the Omega (Ω) field-effect transistor (FET), or simply omega-FET, since the gate electrode 106 has an omega-shape in its cross-sectional view. The encroachment of the gate electrode 106 under the semiconductor fin or body 102 forms an omega-shaped gate structure. This encroachment results in notch or undercut region 132 as shown in FIG. 2c. It closely resembles the Gate-All-Around (GAA) transistor for excellent scalability, and uses a very manufacturable process similar to that of the double-gate or triple-gate transistor.
The omega-FET has a top gate, adjacent surface 110, two sidewall gates, adjacent sidewalls 108, and special gate extensions or encroachments 118 under the fin-like semiconductor body 102. The omega-FET is therefore a field effect transistor with a gate electrode 106 that almost wraps around the body. In fact, the longer the gate extension, i.e., the greater the extent of the encroachment E, the more the structure approaches or resembles the gate-all-around structure. The encroachment of the gate electrode 106 under the silicon body 102 helps to shield the channel from electric field lines from the drain and improves gate-to-channel controllability, thus alleviating the drain-induced barrier lowering effect and improving short-channel performance.
The multiple-gate transistor structures described, e.g., the double-gate transistor, the triple-gate transistor, and the omega-FET, have a common feature: a gate electrode 106 that straddles across the fin-like semiconductor active region 102. The formation of the gate electrode 106 involves a definition step using techniques such as photolithography, and an etching step. The formation of the gate electrode 106 over a large step height introduced by the semiconductor fin 102 presents a very challenging problem. For example, if the top surface of the gate electrode 106 is not substantially flat, the patterning of the gate electrode using lithographic methods can be difficult due to focusing problems.
FIG. 3 shows a prior art process for forming a gate electrode 106 in a multiple-gate transistor. In FIG. 3a, a gate electrode material 120 is deposited over a semiconductor fin 102 and covered with a gate dielectric 110. As shown, the top surface of the gate electrode material 120 is non-planar due to the fin 102.
A mask material 122 such as a photoresist is then deposited on the gate electrode material 120, as shown in FIG. 3b. The top surface of the mask material is usually a planar surface. As a result, the thickness of the mask material varies from t1 in one region to t2 in another region.
A lithographic mask 124 that includes an opaque region 126 and a transparent region 128 will be used to pattern the mask material 122. The pattern on the lithographic mask 124, however, may not be accurately transferred to the mask material 122 due to the varying thickness of the mask material 122. As a result, the patterned mask material 130 may be formed with different widths, as shown in FIG. 3c. When the gate electrode material 120 is subsequently etched, as shown in FIGS. 3d and 3e, the gate electrode 106 may be formed with a non-uniform gate length. The uniformity of the critical gate length dimension is therefore adversely affected.
The present invention provides simple and improved methods for the formation of the gate electrode in a multiple-gate transistor.